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Bhavana Maddu

Electronic Design Automation (EDA),
SIEMENS, Portland, OR USA

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About Me

I work for Semiconductor

We are digital implementation team inside Siemens. Our mission is to integrate latest process technology with most updated commercial design content (CPU, GPU, DSP, etc.) to demonstrate expected performance, power, and area (PPA) improvement. Our results and developed flows are references for worldwide 1st tier design houses.

  • Name

    Age

    Occupation

    Company

    Place

    Education

  • Bhavana Maddu

    25 Years

    Application Engineer

    Siemens EDA

    Portland, OR USA

    MS in Electronics

  • Height

    Weight

    Phone

    Email

    Nationality

    Visa Type

  • 5'4" / 162.56 cm

    70 kgs / 154.324 lb

    +1 971-428-4577

    Indian

    H1-B (USA)

2

Years of
Experience

10 +

Academic
Projects

5 +

Total
Projects

Album

Photo Gallery

Work Experience

My Experience

  • IC Design Technology
    Siemens EDA ( 2024 - Running )

    8005 Boeckman Rd, Wilsonville, OR 97070, United States

  • Digital Marketing
    Webew Technologies ( 2021 - 2022 )

    Webew Technologies Pvt Ltd, Bharathpet, Guntur

  • Web Developer
    Webew Technologies ( 2020 - 2021 )

    Webew Technologies Pvt Ltd, Bharathpet, Guntur

Education

My Education

My educational journey has had good and challenging experiences. For the most part, my educational journey was positive.

  • Masters in Electronics
    Portland State University ( 2022 - 2024 )

    1825 SW Broadway, Portland, OR 97201, Phone: 503-725-3000

  • B.Tech in Electronics & Communication Engineering
    RVR&JC College ( 2017 - 2021 )

    Chowdavaram, Guntur, Andhra Pradesh, 522019, INDIA.

  • Intermediate (10+2)
    Chaitanya College ( 2015 - 2017 )

    Sri Chaitanya Junior College, Dhana Lakshmi campus, Guntur

My Skill

Growing Over Times

Software Development
System Application
Data Administration
Soft Skills

What I Do

Highest Degree

Master's in Electrical & computer engineering, specialization in Design verification & validation track

Recent Project

Designing a synthesizable RPN Calculator (Reverse Polish Notation) and verifying it with a UVM based testbench environment.

Verilog and Digital Design

Training and Hands-on experience in Verilog and Digital Design. Applied concepts like Verification flow, Self-Checking testbench, Randomization, Synchronous FIFO, Verilog Design and Verification.

Skills

Functional Verification, Gate Level Simulation, Building modular, reusable testbenches, implementing coverage-driven verification, and leveraging transaction-level modeling in system Verilog, Very-Large-Scale Integration

Testimonials

What People Say

She is my first friend, my best friend, and my forever friend. My sister is my treasure, the women that keep me grounded. My sister and I, we are just like a really small gang.
Jessy,

Sister

My daughter is my biggest achievement. She is a little star and my life has changed so much for the better since she came along. In my life, you are the sun that never fades and the moon that never wanes.
Anila,

Mother

There is this girl who stole my heart and she calls me Daddy. Behind every great daughter is a truly amazing dad. Being a daddy’s girl is like having permanent armor for the rest of my life.
MS Nivas,

Father

Contact Me

Let’s Connect Together!

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